The present application relates generally to computer system performance adaption. More specifically, the present application is directed to adaptive power capping in a chip of a processing system.
High performance and high reliability computer systems typically require redundancy. However, redundant power system components are expensive, and there is a trade-off between initial system cost and operation under loss of redundancy. When redundancy is lost for power supply components, power (or electric current) must be limited to protect against exceeding component specifications to avoid adverse results. In some systems, a loss of redundancy in power distribution can cause a sudden power-down or chip failure if the current demand exceeds power component limits. Reducing system performance by lowering clock frequency and voltage is one option to avoid exceeding component specifications by assuming worst case conditions; however, system performance may be reduced for a substantial period of time until system maintenance/repair is performed.